1. Field of the Invention
The present invention relates to a semiconductor device including an MIS (metal-insulator-semiconductor) transistor and a method of manufacturing the same.
2. Background Art
Generally, in an MIS transistor including a gate sidewall, the salicide junction leak margin is degraded due to a shallower junction of a source and drain layer. In order to prevent this, an elevated source and drain structure, in which source and drain regions are elevated above a silicon substrate using selective epitaxial growth.
However, since an MIS transistor is isolated using the STI (Shallow Trench Isolation) method, a facet is formed at the boundary between an STI (Shallow Trench Insulator) and an elevated source or drain. Because of such facets, the source and drain regions are partially deepened, resulting in that the aspect ratio between the gate length and the depth of the source and drain regions (junction depth) is smaller in a region under a facet 15a than that in the other regions in the device region. Accordingly, there is a problem in that the short channel effect of the MIS transistor is degraded further (Jie. J. Sun et al., “Impact of Epi Facets on Deep Submicron Elevated Source/Drain MOSFET Characteristics”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, No. 6, June 1998).